The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnection pattern, particularly wherein submicron vias, contacts and trenches have high aspect ratios due to miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, such as undoped monocrystalline silicon, and a plurality of sequentially formed inter-layer dielectrics and patterned metal layers. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnecting lines, such as bus lines, bit lines, word lines and logic interconnecting lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via opening, while a conductive plug filling a contact opening establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor "chips" comprising five or more levels of metallization are becoming more prevalent as device geometries shrink into the deep submicron range.
A conductive plug filling a via opening is typically formed by depositing an inter-layer dielectric on a patterned conductive (metal) layer comprising at least one metal feature, forming an opening in the inter-layer dielectric by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the inter-layer dielectric is removed by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves the formation of an opening which is filled in with a metal. Dual damascene techniques involve the formation of an opening comprising a lower contact or via opening section in communication with an upper trench opening section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
High performance microprocessor applications require rapid speed of semiconductor circuitry.
The speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. As the length of metal interconnects increases and cross-sectional areas and distances between interconnects decrease, the RC delay caused by the interconnect wiring increases. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As design rules are reduced to about 0.18 micron and below, e.g., about 0.15 micron and below, the rejection rate due to integrated circuit speed delays severely limits production throughput and significantly increases manufacturing costs. Moreover, as line widths decrease, electrical conductivity and electromigration resistance become increasingly important.
Cu and Cu alloys have received considerable attention as a replacement material for aluminum (Al) in interconnect metallizations. Cu is relatively inexpensive, has a lower resistivity than Al, and has improved electrical properties vis-a-vis W. Accordingly, Cu is a desirable metal for use as a conductive plug as well as wiring.
Electroless plating, and electroplating of Cu and Cu alloys offer the prospect of low cost, high throughput, high quality plated films and efficient via, contact and trench filling capabilities.
Electroless plating, generally involves the controlled autocatalytic deposition of a continuous film on the catalytic surface by the interaction in solution of a metal salt and a chemical reducing agent. Electroplating comprises the electrodeposition of an adherent metallic coating on a electrode employing externally supplied electrons to reduce metal ions in the plating solution. A seed layer is required to catalyze electroless deposition or to carry electrical current for electroplating. For electroplating, the seed layer must be continuous. For electroless plating, very thin catalytic layers, e.g., less than 100 .ANG., can be employed in the form of islets of catalytic metal.
An approach to forming Cu plugs and wiring comprises the use of damascene structures employing CMP, as in Teong, U.S. Pat. No. 5,693,563. However, due to Cu diffusion through the dielectric interlayer, Cu interconnect structures must be encapsulated by a diffusion barrier layer.
Typical diffusion barrier materials include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium-tungsten (TiW), titanium-titanium nitride (Ti-TiN), tungsten (W), tungsten nitride (WN), and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the dielectric interlayer, but includes interfaces with other metals as well.
Additional problems attendant upon conventional Cu interconnect methodology stem from poor adhesion of a capping layer on the exposed planarized Cu or Cu alloy surfaces. Consequently, the capping layer is vulnerable to removal, as by peeling due to scratching or stresses resulting from subsequent deposition of layers. As a result, Cu or the Cu alloy is not entirely encapsulated and Cu diffusion occurs, thereby adversely affecting device performance and decreasing the electromigration resistance of the Cu or Cu alloy interconnect member. In U.S. Pat. No. 5,447,887, the adhesion problem of a silicon nitride capping layer to a Cu interconnect is addressed by initially treating the exposed surface with silane in the absence of a plasma to form a thin layer of copper silicide, and depositing a silicon nitride capping layer thereon.
As design rules are scaled down into the deep submicron range, e.g., about 0.18 microns and under, the reliability of encapsulated Cu and/or Cu alloy interconnect members becomes increasingly significant. It was found that conventional practices in forming a Cu and/or Cu alloy interconnect member in a damascene opening results in the formation of a thin copper oxide surface film, believed to comprise a mixture of CuO and Cu.sub.2 O. It is believed that such a thin copper oxide surface layer forms during CMP. The thin copper oxide surface film layer is porous and brittle in nature. The presence of such a thin copper oxide surface film undesirably reduces the adhesion of a capping layer, such as silicon nitride to the underlying Cu and/or Cu alloy interconnect member. Consequently, cracks are generated at the Cu or Cu alloy/copper oxide interface, thereby resulting in copper diffusion and increased electromigration as a result of such diffusion. The cracks occurring in the Cu or Cu alloy/copper oxide interface enhance surface diffusion, which is more rapid than grain boundary diffusion or lattice diffusion. The silane treatment disclosed in U.S. Pat. No. 5,447,887, issued to Filipiak et al., generates a thin copper silicide layer on the underlying Cu interconnect member which improves adhesion of a silicon nitride capping layer thereto, but does not address or solve the diminution in adhesion attributable to the presence of the thin copper oxide surface film, which adversely affects adhesion of the capping layer thereon. In copending U.S. patent applications: Ser. No. 09/112,158 filed on Jul. 9, 1998; Ser. No. 09/112,472 filed on Jul. 9, 1998; and Ser. No. 09/112,161 filed on Jul. 9, 1998, techniques are disclosed for removing the oxide layer formed on a Cu or Cu alloy line formed as a result of CMP prior to depositing the capping layer with an attendant improvement in the adhesion of the capping layer to the Cu metalization.
There are, however, further problems attendant upon Cu metallization, particularly when reducing the spacing between Cu or Cu alloy interconnect members, such as lines, to a distance of about 0.10 to about 0.50 micron, e.g., about 0.25 to about 0.50 micron. It was found that as the Cu or Cu alloy lines are formed closer and closer together, in-line diffusion of Cu occurs between neighboring Cu and/or Cu lines which results in shorting therebetween.
Accordingly, there exists a need for a semiconductor device having submicron features and a Cu or Cu alloy interconnect pattern with reduced Cu diffusion between interconnect features. There also exists a need for cost effective, efficient methodology for manufacturing a semiconductor device having submicron features and a Cu or Cu alloy interconnect pattern comprising closely spaced apart neighboring lines with reduced in-line Cu diffusion.